index.md (1292B)
1 +++ 2 title = 'Data dependencies' 3 +++ 4 # Data dependencies 5 instructions: 6 - Add R2, R3, #100 7 - Subtract R9, R2, #30 8 9 R2 is destination for add, and source for subtract 10 11 there is a data dependency between the instructions 12 13 subtract has to be stalled, like this: 14 15 1. Control circuit recognises data dependency when it decodes subtract instruction (compare source/destination registers) 16 17 2. Subtract instruction is held in interstage buffer B1 during cycles 3-5 18 19 3. Add instruction proceeds, signals are set in interstage buffer B2 for implicit NOP (no operation) instruction — creates a ‘bubble’ (clock cycle of idle time) 20 21  22 23 the stalls can be alleviated using operand forwarding: 24 25 - in the above example, value is available at the end of cycle 3 26 - hardware implementation 27 - hardware can forward the value from RZ to where it’s needed 28 - modification of datapath needed (new multiplexer) 29 - software implementation 30 - compiler can identify dependencies and insert NOPs 31 - does not decrease time, increases code size 32 - but hardware isn’t as complicated 33 34 the result of hardware implementation looks like this: 35 36  37 38 The new datapath, incorporating operand forwarding: 39 40 